The present disclosure herein relates to a display device, and more particularly, to a display device according to the interface between a timing controller and a data driving unit.
A display device includes a display panel for displaying images, and a gate driving unit and a data driving unit for driving the display panel. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines. The gate lines receive gate signals from the gate driving unit. The data lines receive data voltages from the data driving unit. The pixels receive the data voltages through the data lines in response to the gate signals received through the gate lines. The pixels display grayscales corresponding to the data voltages, and images are thus displayed.
Furthermore, the display device may include a timing controller for controlling the gate driving unit and the data driving unit. The timing controller may generate a plurality of driving signals for controlling the gate driving unit and the data driving unit, such as in response to external control signals. The timing controller may transfer the data driving signals and a plurality of image signals to the data driving unit, such as through the interface with the data driving unit.
Prior to the interface between the timing controller and the data driving unit, the data driving unit performs a clock data recovery (hereinafter, referred to as CDR) operation. In this case, the timing controller may provide the data driving unit with a clock synchronizing signal to control the performance of the CDR operation by the data driving unit. For example, the data driving unit may perform the CDR operation in response to the clock synchronizing signal in an activated state. The timing controller provides the data driving unit with the driving signals and the image signals after the CDR operation of the data driving unit has been completed.